This describes a controller that makes a synchronous DRAM (SDRAM) appear to operate like a simple static RAM.
The XSA Board synchronous DRAM (SDRAM) controller core accepts simple read and write requests on the host-side and generates the timed waveforms required to perform these operations on the SDRAM. With pipelining enabled, read and write operations within a row of the SDRAM can be dispatched almost every clock cycle. The controller also manages the refresh operations needed to keep the SDRAM data valid, and will place the SDRAM in a self-refresh mode so data is retained even if the controller ceases operation.
A simple example that writes the SDRAM with random data and then verifies it is provided to show how the SDRAM controller is used.
This example design was developed using the following version of software:
Xilinx WebPACK : 6.3.03i
You can download the source files for this example design from the XESS website at /projects/sdramtst-1_4.zip .
Dave Vanden Bout, X Engineering Software Systems Corp.
Send bug reports to firstname.lastname@example.org.
Copyright 2006 by X Engineering Software Systems Corporation.
This application can be freely distributed and modified as long as you do not remove the attributions to the author or his employer.
04/06/2006 - Initial release.